1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, including a process of forming a laminated insulating film which comprises an insulating film including silicon, carbon, nitrogen, and hydrogen, and an insulating film including silicon, carbon, oxygen, and hydrogen.
2. Description of the Related Art
Accompanying high-integration and increase in speed of semiconductor devices, reductions of an inter-wiring capacitance and an interlayer capacitance are required. Therefore, developments of techniques for making a low resistance metal wiring and techniques for making a low dielectric insulating film have progressed.
As the techniques for making the low dielectric interlayer insulating, there is an example of an introduction of an SiOC:H film which has a relative dielectric constant lower than that of an SiO2 film which has been conventionally used and which is one of the so-called low dielectric constant interlayer insulating films (Low-k films).
When a Cu wiring is formed at the inside of the SiOC:H film by a dual damascene wiring process, a stopper film is formed in advance on a Cu wiring (lower layer Cu wiring) which is at the lower layer of the Cu wiring.
The reason for this is that the lower layer Cu wiring is not damaged by etching in a process of etching for opening a via hole in the SiOC:H film. Another reason is for suppressing the diffusion of Cu into the interlayer insulating film.
As a stopper film, an SiN film has been conventionally broadly used. However, the relative dielectric constant (relative permittivity) of the SiN film is about 7 and high. Therefore, in recent years, developments of insulating films such as an SiC film, an SiCO film, an SiCN film, and the like have been made to progress. Thereamong, attention has focused on the SiCN film because the SiCN film has an etching rate which is sufficiently lower than that of the SiOC film, and is superior with respect to the etching selectivity, and moreover, is superior also with respect to the relative dielectric constant and the leakage characteristic.
However, in a case of a dual damascene process in which a via hole is formed in advance, in the process of forming a via hole in the SiOC:H film, a concentration of a material (NxHy; x and y are positive integers) having an alkalinity such as NH2 including nitrogen and hydrogen, or the like, becomes high.
This type of NxHy can be the reason for inhibiting the resolution of a resist which will be a resist pattern for forming a wiring trench which is formed after forming the via hole, in particular, a chemically amplified resist. This is because the acid generated at the exposed portion of the resist is neutralized, and the dissolution thereof is inhibited.
Therefore, a predetermined-shaped resist pattern for forming a wiring trench cannot be formed, and the problem that it is difficult to form a predetermined-shaped wiring arises (for example, Document 1 (Overcoming of resist poisoning issue during Si—O—C dielectric integration in Cu Dual Damascene interconnect for 0.1 μm technology, M. Fayolle, G. Fanget, J. Torres, and G. Passemard, Proceedings of Advanced Metallization Conference (AMC) 2001, US Session, Montreal (Canada), Oct. 9–11, 2001, p.209), Document 2 (Integration of Cu/SiOC in Dual Damascene interconnect for 0.1 μm technology using a new SiC material as dielectric barrier, M. Fayolle, J. Torres, G. Passemard, F. Fusalba, G. Ganget, D. Louis, L. Arnaud, V. Girault, J. Cluzel, H. Feldis, M. Rivoire, O. Louveau, T. Mourier, and L. Broussous, Proceedings of the 2002 Internatinal Interconnect Technology Conference, San Francisco (Calif., USA), Jun. 3–5, 2002, p.39), and Document 3 (Via First Dual Damascene integration of Nanoporous Ultra Low-k Material, J. C. Lin, H. S. Lee, S. Satyanarayana, H. Martinz, T. Jacobs, K. Brennan, A. Gonzalez, R. Augur, S. L. Shue, C. H. Yu, and M. S. Liang, Proceedings of the 2002 International Interconnect Technology Conference, San Francisco (Calif., USA), Jun. 3–5, 2002, p.48)).
Provided that a dual damascene process in which a wiring trench is formed in advance is used, there is no need to concern the problem about the deterioration in the resolution of the resist. However, in the dual damascene process in which a wiring trench is formed in advance, another problem which does not exist in the dual damascene process in which a via hole is formed in advance exists, and it is not the case that all of the problems are solved by using a dual damascene process in which a wiring trench is formed in advance.